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HI-1818A
Data Sheet November 19, 2004 FN3141.4
Low Resistance, Single 8-Channel, CMOS Analog Multiplexer
The Hl-1818A is a monolithic, high performance CMOS analog multiplexer offering built-in channel selection decoding plus an inhibit (enable) input for disabling all channels. Dielectric Isolation (Dl) processing is used for enhanced reliability and performance. Substrate leakage and parasitic capacitance are much lower, resulting in extremely low static errors and high throughput rates. Low output leakage (typically 0.1nA) and low channel ON resistance (250) assure optimum performance in low level or current mode applications. The HI-1818A is a single-ended, 8-Channel multiplexer, and is ideally suited for medical instrumentation, telemetry systems, and microprocessor based data acquisition systems.
Features
* Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V * "ON" Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 * Input Leakage (Max) . . . . . . . . . . . . . . . . . . . . . . . . .50nA * Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350ns * Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . .5mW * DTL/TTL Compatible Address * Operation . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Applications
* Data Acquisition Systems * Precision Instrumentation * Demultiplexing * Selector Switch
Ordering Information
PART NUMBER HI1-1818A-2 TEMP. RANGE (oC) -55 to 125 PACKAGE 16 Ld CERDIP PKG. DWG. # F16.3
Pinout
HI-1818A (CERDIP) TOP VIEW
ADDRESS A1 1 +5V SUPPLY 2 ENABLE 3 ADDRESS A2 4 IN 8 5 IN 7 6 IN 6 7 IN 5 8 16 ADDRESS A0 15 -VSUPPLY 14 +VSUPPLY 13 IN 1 12 OUT 11 IN 2 10 IN 3 9 IN 4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002, 2004. All Rights Reserved
HI-1818A Truth Table
HI-1818A TRUTH TABLE ADDRESS A2 L L L L H A1 L L H H L A0 L H L H L EN L L L L L "ON" CHANNEL 1 2 3 4 5 A2 H H H X HI-1818A TRUTH TABLE ADDRESS A1 L H H X A0 H L H X EN L L L H "ON" CHANNEL 6 7 8 None
Functional Block Diagram
HI-1818A
DIGITAL ADDRESS ENABLE A0 ADDRESS INPUT BUFFERS A1 A2
ENABLE BUFFER
MULTIPLEX SWITCHES N P
IN 1
DECODERS OUT IN 8 N P
Schematic Diagrams
ADDRESS INPUT BUFFER
P3
P5 P1 V+ D1 200 N1 VCC P4 A P6 D2 ADDRESS INPUT VP2 N2 N5 N6 N4 A N7 N8 N9 N10 P7 P8 P9 P10
All N-Channel Bodies to VAll P-Channel Bodies to V+ Unless Otherwise Specified
N3 V-
2
FN3141.4 November 19, 2004
HI-1818A Schematic Diagrams
ADDRESS DECODER
V+ EN P11 A2 OR A2 A1 OR A1 P13 A0 OR A0 P14 P15 P16 TO N-CHANNEL SWITCH N11 N12 N13 N14 N15 N16 P12 TO P-CHANNEL SWITCH
All N-Channel Bodies to VAll P-Channel Bodies to V+
V-
IN SWITCH CELL
MULTIPLEXER SWITCH
FROM DECODE
N18
All N-Channel Bodies to VAll P-Channel Bodies to V+ Unless Otherwise Specified
V+
N17 OUT V+ P18
IN
N19 P17
FROM DECODE
3
FN3141.4 November 19, 2004
HI-1818A
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . (V-) to (V+)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 80 20 Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
Electrical Specifications
DYNAMIC CHARACTERISTICS Access Time, tA Break-Before-Make Delay, tOPEN Enable Delay (ON), tON(EN) Enable Delay (OFF), tOFF(EN) Settling Time
Supplies = +15V, -15V, +5V; VAL = 0.4V, VAH = 4.0V, Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS
PARAMETER
Note 4
25 Full 25 25 Full 25 Full
-
350 25 300 300 1.08 2.8 4 20 0.6 5
500 1000 500 1000 500 1000 -
ns ns ns ns ns ns ns s s pF pF pF pF
To 0.1% To 0.025%
25 25 25 25 25 25
Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) Input to Output Capacitance, CDS(OFF) Digital Input Capacitance, CA DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Input High Threshold, VAH Input Leakage Current, IA ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VlN ON Resistance, rON OFF Input Leakage Current, IS(OFF) ON Channel Leakage Current, lD(ON) OFF Output Leakage Current, ID(OFF) Note 2 Note 3
Full Full Full
4.0 -
-
0.4 1
V V A
Full 25 Full Full Full Full
-15 -
250 -
+15 400 500 50 250 250
V nA nA nA
4
FN3141.4 November 19, 2004
HI-1818A
Electrical Specifications
Supplies = +15V, -15V, +5V; VAL = 0.4V, VAH = 4.0V, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS
PARAMETER POWER SUPPLY CHARACTERISTICS Power Dissipation, PD Current, I+ Current, ICurrent, IL NOTES: 2. VOUT = 10V, IOUT = 1mA.
Full Full Full Full
-
-
27.5 0.5 1 1
mW mA mA mA
3. To drive from DTL/TTL circuits, 1k pull-up resistors to 5.0V supply are recommended. 4. Time measured to 90% of final output level; VOUT = -5.0V to 5.0V, Digital Inputs = 0V to 4.0V.
Test Circuits and Waveforms
+15V -15V +5V
A2 V+ VAH = 4.0V 50% VAL = 0V tON (EN) 90% 10% tOFF (EN) VA 50 ENABLE DRIVE (VA) OUTPUT A1 A0 EN
V-
VL +5V
IN 1 HI-1818A IN 2-8 OUT 200
ENABLE DRIVE 2V/DIV.
ENABLED (S1 ON) 12.5 pF DISABLED OUTPUT 2V/DIV.
100ns/DIV.
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT FIGURE 1. ENABLE DELAYS
FIGURE 1C. WAVEFORMS
+15V -15V +5V
A2 V+ 4.0V ADDRESS DRIVE (VA) 50
V-
VL IN 1 IN 2 +5V S1 ON
VA INPUT 2V/DIV. S2 ON
A1 HI-1818A EN
0V
IN 3-8 A0 VA OUT 200 12.5 pF OUTPUT 1V/DIV.
50%
50% OUTPUT tOPEN
100ns/DIV.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT FIGURE 2. BREAK-BEFORE-MAKE DELAY
FIGURE 2C. WAVEFORMS
5
FN3141.4 November 19, 2004
HI-1818A
1mA
V2
IN OUT VIN 350 RON = OUT V2 1mA 60 40 20 V
A
-55oC 125oC 25oC
125oC 250 25oC 200 -55oC
SWITCH CURRENT (mA)
300 ON RESISTANCE ()
0 -20 125oC -40 -60 -55oC -10 -8 -6 25oC -4 -2 0 2 4 6 VOLTAGE ACROSS SWITCH (V) 8 10
150
100 -10
-8
-6
-4
-2 0 2 4 ANALOG INPUT (V)
6
8
10
FIGURE 3. ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 4. ON CHANNEL CURRENT vs VOLTAGE
OFF LEAKAGE EN 4V OUT
ON LEAKAGE +5V OUT A ID(OFF) EN A1 A ID(ON) 10V 0.4V
ACCESS TIME TEST CIRCUIT IN 1 OUT 10 k 50pF
IN 2 -5V IN 3-8 HI-1818A A0 A1 A2 EN
10V
+10V
+10V
A0
NOTE:
IS(OFF) A 10V +10V EN OUT 4V
0V TO 4V
50
Two measurements per channel: 10V and 10V Two measurements per device for ID(OFF): 10V and 10V
100nA 4V 10nA ID(ON) - ID(OFF) HI-1818A 1nA IS(OFF) 100pA HI-1818A 10% 10pA 25 50 75 TEMPERATURE (oC) 100 125 tA 100ns/DIV. +5V OUTPUT 5V/DIV. -5V A0 INPUT 50% 2V/DIV.
FIGURE 5. LEAKAGE CURRENTS vs TEMPERATURE
FIGURE 6. ACCESS TIME
6
FN3141.4 November 19, 2004
HI-1818A Die Characteristics
METALLIZATION: Type: CuAl Thickness: 16kA 2kA PASSIVATION: Type: Nitride/Silox Thickness: Silox: 12kA 2kA, Nitride: 3.5kA 1kA WORST CASE CURRENT DENSITY: 1.43 x 105 A/cm2 at 25mA
Metallization Mask Layout
HI-1818A
VL A1 A0 -VSUPPLY
EN
A2
+VSUPPLY IN 1
IN 8
OUTPUT
IN 7 IN 6 IN 5 IN 4 IN 3 IN 2
7
FN3141.4 November 19, 2004
HI-1818A Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 8
FN3141.4 November 19, 2004

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